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Espressif Systems /ESP32-S2 /SENS /SAR_READER1_CTRL

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Interpret as SAR_READER1_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SAR1_CLK_DIV0 (SAR1_CLK_GATED)SAR1_CLK_GATED 0SAR1_SAMPLE_NUM0 (SAR1_DATA_INV)SAR1_DATA_INV 0 (SAR1_INT_EN)SAR1_INT_EN

Description

RTC ADC1 data and sampling control

Fields

SAR1_CLK_DIV

Clock divider.
SAR1_CLK_GATED
SAR1_SAMPLE_NUM
SAR1_DATA_INV

Invert SAR ADC1 data.
SAR1_INT_EN

Enable SAR ADC1 to send out interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data